1. Field of the Invention
The invention relates to interprocessor communications. More specifically, the invention concerns enabling communications between dissimilar processor buses while increasing performance and reducing CPU overhead.
2. Background Art
Banks, credit unions and other financial institutions often image checks, deposit slips and other types of bank documents in order to process financial transactions efficiently. Document processing systems have therefore become quite prevalent in the industry. In the performance of these critical functions, document processing systems commonly contain multiple microprocessor elements that are responsible for performing different tasks within the machine. In addition to their individual processing responsibilities, these processor elements are often required to communicate with each other.
A common difficulty, however, arises when there is a need to communicate between processors operating on dissimilar buses. Typically, the respective tasks of processors in an embedded dual processor controller board will involve the processing of substantially dissimilar signals. Common schemes fail to adequately address this problem and do not incorporate the ability to allow direct memory access (DMA) to occur on the two dissimilar buses simultaneously. Approaches attempting to address this problem have resulted in complex board designs leading to increased costs and reduced performance.
Furthermore, it is often difficult to determine the source of an error when two processors are communicating via dissimilar buses. It is therefore also desirable to provide the ability to troubleshoot communication errors in these types of inter-processor configurations without significantly adding to costs.
In a first aspect of the invention, a processor bus bridge comprises a buffer space disposed between a first bus and a second bus. The first bus is operated in a first mode by a first processor and the second bus is operated in a second mode by a second processor. The first bus has an electrical structure which is different from the electrical structure of the second bus. The processor bus bridge also comprises a protocol logic module disposed between the first processor and the second processor for controlling data transfer across the buffer space in the first and second modes.
In a second aspect of the invention, a method for interprocessor communication comprises the steps of operating a first bus in a first mode, wherein the first bus is connected to a first processor and operating a second bus in a second mode. The second bus is connected to a second processor, wherein the first bus has an electrical structure which differs from the second bus. The method also comprises the step of transferring the data between the first processor and the second processor via the first bus, the second bus, and a processor bus bridge.